Specification Development Effort Purpose
Enable foundry and assembly test partners to deliver semiconductor test data to chip designers. The purpose is to gain efficiencies by defining a common vocabulary and structure for the transmission of test data. This standard will help reduce design development time by providing globally standard data in a commonly understood manner.

Specification Development Effort Scope
1) Define and document requirements to support the sending of test result information to a trading partner for the following semiconductor tests:

 a. Wafer Acceptance Test Data (WAT)–   The data resulting from the testing of a sample of chips on a semiconductor wafer to determine if chips meet engineering specifications. For a foundry environment, this test data provides the ‘go’ or ‘no go’ decision to determine if the wafer passes or fails the agreed upon wafer acceptance criteria.  This test data is limited to data produced from testing individually wired devices / structures built in the 'dicing channel' versus the functional / integrated die on the entire wafer.

b. Wafer Sort Data (Wafer Probe) – The data resulting from the functional testing for each functional / integrated die on the entire wafer .  These test data results may be shared as either reconciled information at the chip summary level or as raw test data   Test results may include parametric measures and quality sort data.

c. Module Final Test Data – The data resulting from the testing of modules to ensure the module functions to the application specifications of the packaged module. This test also includes parametrics and quality sorts data. 

2) Define, document and align a common vocabulary for sending these three semiconductor test data sets.

3) Validate and implement the PIP(s) with multiple partners.

The program scope DOES NOT include plans to:
          · Define the process of acquiring or aggregating the test data
          · Define and document the exchange of data for the following business process areas:
                     - Process Data: film thickness, overlay & CD or resistivity
                     - Defect Data: defect classification
                     - FCS Logistics: wafer history/operation, tools, recipes, rework, holds, etc.
          · Define a business acknowledgement reply for the reception of the data
          · Redefine or develop any vocabularies or formats already existing in the market today that can be used by RosettaNet

Specification Development Expected Output
          · Specification Requirements Documents for exchanges defined in the scope description
          · eBusiness Process Description for each expected PIP as well as one for the overall data exchange process
          · Validated XML Schema PIP(s) for exchanging semiconductor test data for:
                    - Wafer Acceptance Test Data
                    - Wafer Sort (or Wafer Probe) Data
                    - Module Final Test Data

Documentation and Implementation Support Expected Output
The supporting business and technical documentation to be developed by the program include:
          - RosettaNet Implementation Guide (RIG)

Include any known relationships or dependencies to other working groups or RosettaNet specifications:
          - RosettaNet Technical Dictionary (RNTD)
          - Convergence opportunity: SEMI (G81, G84 and G85)